Now that the entire series is done I’ve figured a small overview would be in order.
Part 1 talks about the different address spaces that a i915 GEM buffer object can reside in and where and how the respective page tables are set up. Then it also covers different buffer layouts as far as they’re a concern for the kernel, namely how tiling, swizzling and fencing works.
Part 2 covers all the different bits and pieces required to submit work to the gpu and keep track of the gpu’s progress: Command submission, relocation handling, command retiring and synchronization are the topics.
Part 3 looks at some of the details of the memory management implement in the i915.ko driver. Specifically we look at how we handle running out of GTT space and what happens when we’re generally short on memory.
Finally part 4 discusses coherency and caches and how to most efficiently transfer between the gpu coherency domains and the cpu coherncy domain under different circumstances.
Update: There’s now also a new article with a few questions and answers about some details in the i915 gem code.