Thursday, March 10, 2016

Neat drm/i915 stuff for 4.6

The 4.5 release is close, it's time to look at what's in store for the next kernel's merge window in the Intel graphics driver.

Headline features for sure are that FBC and PSR are enabled by default. And this time around I'm really hopeful that it will stick, since Paulo&Rodrigo have done a stellar job hunting down all the corner cases, writing testcases for them all and in general making sure we have a really solid foundation for display power saving features. There's still some oddball cornercases, which means it's not yet enabled everywhere and on all platforms, but like I said: Looking really good, and the culmination of over 1 year of effort to get the code infrastructure fixed up and solid.

Another project ongoing is atomic display support, with again lots of work from Maarten and Matt and others to move things forward. Specifically Maarten adapted the load detect logic to atomic and removed a pile of legacy structures no longer needed in preparation of next steps. Matt continued to work on atomic display fifo watermark updates. Another area that has seen a lot of work in the background is runtime PM. Mika, Imre and Ville have massively improved the debugging infrastructure we have to track down rare bugs in our power status tracking code. They also merged lots of fixes in this area. Unfortunately we're not yet at a point where we can enable overall runtime PM for the device by default.

More on the feature side is pixel clock limit checks for all outputs and platforms from Mika Kahola. This is related to the work to also enable dynamic display clock scaling on Gen9, but that part is still being worked on. Ville worked a lot on how offsets and alignment are handled for display planes, all in preparation to support rotated multi-planar formats like NV12. Again a feature where a lot of hard work is required to make the final patch to enable it all look really simple.

On the plain hardware and platform enabling side Jani implemented support for version 3 of the VBT DSI descriptions, which should extend DSI panel support to all current hardware. Which includes the Surface 3.

Finally on the GEM side there have been mostly small fixes and imrpovements under the hood. Tvrtko decoupled the internal engine representation from the userspace ABI defines. He also restructed the CS irq handler code, and started to fix up some locking issues in execlist. Chris tracked down some coherency issues in the execlist interrupt handler. Dave Gordon finally started to somewhat untangle the execlist initialization logic and some of the confusion in how all the different software structures connect.

One real feature work by Alex Dai though was enabled ADS for GuC, which is some means to hand additional metadata to the GuC firmware scheduler. But since GuC based command submission isn't enabled yet, this doesn't have a direct impact.

And of course there have been bugfixes all over the place, as usual.

2 comments:

  1. Kindly kind of repeating the question by the other user on the "neat stuff for 4.5" really out loud: Does this include the kernel patches to support Quick Sync transcoding in Linux? Intel media group says out loud that "No, we do not upstream our Media-specific patches to the kernels" (https://software.intel.com/en-us/forums/intel-media-sdk/topic/550989) so it is not about marketing only. Please answer a) Yes patches are includes b) Patches are not included c) I'm not in liberty to tell. FYI there are 0 known implementations of use of the MFX transcoder based on OSS.

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  2. Hi,
    I own a netbook with a good old GMA 950 (Gen3 or Gen3.5 in Intel glossary) with few hardware decode capabilities (MPEG-2 motion compensation unless I am mistaken, which doesn't help for DivX movies for instance).
    Will that graphical processor benefit from atomic mode-setting so that I can hope for better battery life while watching videos (dealing with YUV videos without RGB conversion is supposed to help) ?
    Thanks !

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